The present invention generally relates to writing data to memory, and, more particularly, to a memory controller for writing data to a memory.
Integrated circuits generally include processors, memory controllers, and memories. Often, a processor writes data (referred to as write data) to a memory by initiating a write transaction to store the write data in the memory. The write transaction includes write control data, the write data, and an address. The write control data includes information such as transaction mode, transaction type, and transaction length. The processor also generates commands such as a write enable command, a memory lock command, an address latch enable command, and the like.
The processor generates and transmits the write transaction and the commands to the memory controller, which executes the write transaction based on the commands, to store the write data in the memory. The memory controller receives the write transaction at an input data rate and stores the write data in the memory at an output data rate. As the processor generates multiple commands for every write transaction, its efficiency decreases, which in turn decreases the input data rate such that it may be less than the output data rate, which introduces latency in the execution of the write transaction.
Paged memories include one or more pages, and each page has a boundary address, which is the last address of the page indicating a page boundary. The write data is stored in the pages of the memory. Typically, when the memory controller stores the write data at a first address of a current page, the processor provides a first boundary address of the current page to the memory controller. In order to store the write data at a second address of the current page, which is consecutive to the first address of the current page, the memory controller compares the second address with the first boundary address. If the second address is not equal to the first boundary address, then the memory controller stores the write data at the second address of the current page. However, if the second address is equal to the first boundary address, the memory controller detects the page boundary and generates a handshaking signal, and then the memory controller writes the write data at a first address of a page that is consecutive to the current page. The processor receives the handshaking signal and provides a second boundary address of the consecutive or next page to the memory controller. Similarly, in order to store the write data at a second address of the next page, which is consecutive to the first address of the next page, the memory controller compares the second address of the next page with the second boundary address. However, the process of handshaking between the processor and the memory controller introduces a delay in providing the second boundary address to the memory controller, and consequently in storing the write data in the next page.
One technique to reduce the latency introduced by the processor is to generate the commands only one time and store them on a dedicated page of the memory. Then, for every write transaction, the memory controller accesses the commands from the memory instead of accessing them from the processor. Since the processor generates commands only once and not for every write transaction, its efficiency increases and the latency in the execution of the write transaction is reduced. However, this does not reduce the delay introduced due to the handshaking between the processor and the memory controller.
Another technique to overcome the aforementioned latency problem is to use a buffer to store the write data and the commands. The memory controller then is connected to the buffer to access and execute the commands. This reduces the latency, but still does not address the current page boundary detection issue.
It would be advantageous to have a memory controller that matches the input data rate with the output data rate and that can detect page boundaries.